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Realizing Deep Learning on FPGA with SDSoC

 

Realizing Deep Learning on FPGA with SDSoC

1.    Course Description

 

This course is specially designed for designers new to DeepLearning design or application. The introduction to the theoretical principle, effective comprehension of training and testing flow using Caffe Framwork, demonstrate impressive project demo, understand the design flow with C/C++ coding techniques, use little HDL coding techniques and more C coding techniques to apply Deeplearning demo on edge of FPGA device. 

 

Comprenhend the theoretical principle, training, testing and process about application on FPGA device allows you to test your knowledge and apply your skills on Deeplearning immediately. You will be able to face the real challenge to do a primary Deeplearning design flow project with the guidance of our instructor.

 

2.    Duration

 

4 days

 

3.    Software Tools

 

Eclipse, Visual Studio, Python, Vivado® Design Suite and SDSoC.

 

4.    Prerequisites

 

Basic knowledge of mathematics, matix and complex function.

 

Program knowledge about C/C++, Python.

 

5.    Course Outline

 

Day 1

 

1.1  Introduction to DeepLearning

 

Overview of DeepLearning origin and development, propose the process and methodology of Deeplearning design.

 

1.2   Introduction to Artifical and Convolutional Neural Network

 

Overview of Convolutional Neural Network and introduces the mathematical model of Artifical Neural Network.

 

1.3   DeepLearning Design Methodology

 

Introduces the methodology guidelines covered the DeepLearning training stage and the design flow.

 

1.4   Introduction to the Architecture of Convolutional Neural Network

 

Introduces the primary network layers in the architecture of Convolution Neural Network.

 

1.5   Installation about Caffe framework

 

Introduces the process of installation about Deeplearning framework Caffe, including the setting of enviroment about caffe, python, etc.

 

1.6   Introduction to network structure files in Caffe

 

Introduces the details of network structure about the Cifar10 demo in Caffe and the basic knowledge for training and testing.

 

1.7   Process on training and testing with the Cifar10 demo

 

Demostrate the process of training and testing with Cifar10 demo, comprehend the implication of data on testing process.

 

1.8   Experiments about Mnist Dataset demo

 

Interactions using experiments about Mnist Dataset demo with Python coding techniques.

 

1.9  Hands-on operation and experiment

 

Day 2

 

2.1  Review

 

Review the foundations about DeepLearning on Caffe.

 

2.2  Introduction to Forward Propagation

 

Introduces the design of Forward Propagation with C coding techniques and demonstrate the Inference demo about Cifar10 demo to identify airplane, automobile, bird, horse, etc.

 

2.3  Introduction to Backward Propagation

 

Introduces the theoretical principle and derivation process about Backward Propagation.

 

2.4  Introduction to training and testing demo

 

Demonstrate the training and testing demo and introduce structures and codes about the demo with C++ coding techniques.

 

2.5  Hands-on operation and experiment

 

Day 3

 

3.1  Introduction to ZYNQ AP SoC

 

Introduces the zynq ap soc: architecture and pl-ps interconnect.

 

3.2  Starting with VIVADO and SDK

 

Introduces the Vivado and SDK design flows: the project flow and non-project batch flow.

 

3.3  Introduction to Xilinx SDK Template

 

Introduces the Xilinx SDK Template and SDK design Simple projects flows.

 

3.4  Using Tcl Commands in the Vivado Design Suite Project Flow

 

Explains what Tcl commands are executed in a Vivado Design Suite and uses Tcl

 

Scripts to create a hardware project . 

 

3.5  Introduction to AXI protocol

 

Introduces the AXI protocol and AXI detail:axi-lite,axi-full,ect...

 

3.6  Hands-on operation and experiment

 

Day 4

 

4.1  SDSoC Tool Overview

 

Explain the advantages of using the SDSoC development environment and describe the typical SDSoC development flow.

 

4.2  Tools Collection

 

Introduces the Tools:sdsoc IDE involes a lot of tools ,CDT,TCF,sdscc/sds++ ...

 

4.3  SDSoC Platform Creation

 

Introduces the SDSoC Platform structure and how to create a new platform

 

4.4  Understanding Estimations in the SDSoC Tool

 

Introduces the Estimations tool in the SDSOC:estimations the source of FPGA when generated a new accelarator.

 

4.5  Pragma Syntax

 

Understand the pragma syntax and Use Pragma to get better performance.

 

4.6  Introduction to Deeplearning demo complete with SDSOC Design Suite

 

Using sdsoc accelerate complex algorithm :complex algorithms are implemented in FPGA .

 

4.7  Hands-on operation and experiment

 

 

 

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